1. Field of the Invention
The present invention relates to a mask for manufacturing a semiconductor device and a method of forming the mask, and more particularly, to a mask for forming a semiconductor device with a fine pattern and a method of forming the mask.
2. Description of the Related Art
With the continuous trend toward higher integration, patterns for forming semiconductor devices continue to gradually become finer. As the sizes of individual devices formed with fine patterns also continue to be reduced, the pitch (that is the width of a pattern and the spacing or interval between patterns) of a desired pattern must also be reduced. However, further reduction of the design rule to form line patterns is generally limited due to a resolution limit of the photolithography process that is used to form the patterns (for example, a line and space pattern—hereinafter referred to as a line pattern) when manufacturing a semiconductor device.
To overcome the resolution limitations of the photolithography process, double patterning methods have been proposed. Double patterning can be implemented in a variety of ways, such as a method of forming spacers of a small size (disclosed in U.S. Pat. No. 6,603,688, which is hereby incorporated by reference) and a self-aligning method (disclosed in Korean Patent Application No. 10-2005-0032297, which is hereby incorporated by reference).
In the double patterning methods, a first pattern is formed in a first direction using a photolithography process, and a second pattern is formed at a predetermined distance from the first pattern, using a method other than a photolithography process, for example, using spacers or a self-aligning method. However, in this approach, the patterns on a mask, especially the second pattern, are actually transferred to an object.
FIGS. 1A and 1B are sectional views for illustrating a fine pattern forming method using a self-aligning method, which is a conventional example of double patterning. Here, regions a and b are regions where the second pattern is prone to defects, and region c is a region where the second pattern is formed normally. Here, the defects refer to regions where the second pattern is not actually transferred to the object properly.
Referring to FIGS. 1A and 1B, a first mask pattern 14 formed using a photolithography process is repeatedly formed on a semiconductor substrate 10 with an etch layer 12 formed thereon. Here, the first mask pattern 14 is used for forming the first mask pattern 12a of the etch layer 12, as shown in FIG. 1B. A first mask layer 18 and a second mask layer 20 are subsequently formed on the semiconductor substrate 10 including the first mask pattern 14. The first mask layer 18 is formed to conformally cover the top and side surfaces of the first mask pattern 14 evenly, and preferably to a thickness that corresponds to a first distance D1 in region c. The second mask layer 20 conformally covers the first mask layer 18 to an even thickness. Here, the second mask layer 20 may be formed of a material having the same etching characteristics as that of the first mask pattern 14.
Next, wet etching is used to remove a portion of the second mask layer 20. As a result, a second mask pattern 20a remains on a recessed portion of the normal region that is region c. Here, the second mask pattern 20a is a mask that is used for forming the second pattern of the double patterning procedure. However, in this example, the second mask pattern 20a is not formed on the defective regions a and b since the second mask layer 20 is entirely removed by the wet etch in the defective regions a and b.
When anisotropic etching is performed after the second mask pattern 20a is formed, a first pattern 12a is formed at the bottom of the first mask pattern 14, and a second pattern 16c is properly formed below the second mask pattern 20a of the normal region c. However, the second mask pattern 20a is not properly formed on the defective regions a and b, and the second patterns 16a and 16b on the mask are therefore not properly transferred onto the semiconductor substrate 10.